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Complex Digital Systems >> Content Detail



Lecture Notes



Lecture Notes

The table below contains information on the course's lectures (L) and tutorials (T). Tutorials 1 and 2 are courtesy of Christopher Batten. Tutorial 3 is courtesy of Michael Pellauer.


Lec #Topics
L1Introduction (PDF - 1.7 MB)
L2Digital Design Using Verilog (PDF)
L3CMOS Technology and Logic Gates (PDF - 2.4 MB)
T1Verilog Simulation I (PDF)
L4Wires (PDF - 1.4 MB)
L5Synthesis (PDF)
T2Verilog Simulation II (PDF)
L6Clocking (PDF)
L7Bluespec I: Motivation (PDF)
L8Bluespec II: Designing with Rules (PDF)
L9Bluespec III: Modules and Interfaces (PDF)
L10Bluespec IV: Rule Scheduling and Synthesis (PDF)
T3Bluespec (PDF)
L11Power (PDF)
L12Bluespec V: Processors (PDF)
L13Bluespec VI: Modularity and Performance (PDF)
L14Transaction Level Design and Verification (PDF)
L15Testing (PDF)

 








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